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Silicon and Beyond

Has the semiconductor revolution run its course? Not quite, say these researchers, who are working on new materials and looking for a miracle or two.

Mark Rodwell

Mark Rodwell, a professor of electrical engineering.

To understand the SRC Nonclassical CMOS Research Center, a joint project of electrical engineering and materials experts from UC Santa Barbara and other leading universities, it helps to know some terminology and some history.

SRC is the Semiconductor Research Corporation, a non-profit consortium funded by technology firms. It supports the Nonclassical CMOS Research Center, set up in 2006, with a 3-year, $7 million grant. CMOS stands for “complementary metal-oxide semiconductor” and refers to transistors made from metal or polysilicon electrodes and oxide (usually silicon dioxide) insulators. The CMOS model is a mainstay of microprocessors, memory and other key elements of modern computing and electronics. “Nonclassical” refers to the center’s mission – to move beyond the standard silicon technology, which is hitting its natural limits. This is where the history comes in.

Mark Rodwell, a UCSB professor of electrical and computer engineering who leads the center’s device-fabrication effort, says the challenges faced today were long foreseeable, and to some degree foreseen, by the silicon industry. Up to now, chipmakers have boosted silicon chip performance mainly through scaling – that is, shrinking the conductors and the spaces between them to shorten the distance traveled by electrons. Rodwell says the principles for this process were set out in the 1970s by IBM scientist Robert H. Dennard and others, and “Dennard’s scaling laws,” as they are called, have been the industry’s rulebook ever since.

Dissolving Walls

Scaling laws dictate certain size ratios for a transistor’s various parts, such as the silicon path for current, the metal or polysilicon “gate electrode” that extends along the path and turns the current on and off, and the oxide insulator between the gate electrode and the path. If the length of the gate electrode shrinks, for instance, the insulator has to be thinner as well. Rodwell says gate lengths in today’s transistors have reached a point, down to about 45 nanometers, where the proportionality rule starts to cause serious problems. The insulator, made from silicon dioxide in classical CMOS, becomes too thin to prevent leakage of electrons to the gate electrode. “It goes to hell in a hand-basket rapidly, right around one nanometer,” he says.

The insulator, made from silicon dioxide in classical CMOS, becomes too thin to prevent leakage of electrons to the gate electrode. “It goes to hell in a hand-basket rapidly, right around one nanometer,” Rodwell says.

Lurking behind the issue of too-thin insulators is a fundamental fact: You can shrink transistors, but you can’t shrink the atoms from which they’re made. That’s no longer just a theoretical problem. Chris Palmstrøm, leading the center’s research on the integration of transistor materials, says device sizes are heading to a scale at which insulators and channels are just a few atoms wide (a silicon atom is about one-fifth of a nanometer in diameter). Not only are they more leaky at this size, they are less definite and predictable. “Part of the problem is that you go from classical physics to quantum mechanics,” says Palmstrøm, who will be moving from the University of Minnesota to the UCSB Materials faculty this year. Structures that acted as solid walls and conduits at larger sizes begin to dissolve into particles moving randomly in indefinite positions. The power needed to keep current flowing where it should is so high that the device overheats. “At some point,” he says, “you can no longer make this thing work classically.”

Non-Silicon Options

So scaling has basic limits and they are being reached now. The good news is that scaling is not the only way to improve semiconductor performance. Manufacturers can use mechanical strain to increase electron mobility by changing the space between silicon atoms. They also know they can get much bigger boosts by using so-called III-V compounds as semiconductors (the roman numerals refer to the number of electrons available for bonding in each of the two combined elements). These are substances, such as Gallium Arsenide or Indium Phosphide, in which two atoms together work like a single atom of silicon but electrons in these materials move much faster, about four times silicon speed. Compound semiconductors are already used in cell phones and other electronics where their relatively high cost and fragility are no barriers. There are non-silicon options in insulators as well. Scientists have been developing new compounds as replacements for silicon dioxide.

Mark Wistey

Graduate student Mark Wistey using the molecular beam epitaxy machine where the III-V materials are fabricated.

These alternative materials are the focus of the center, which draws on faculty and facilities at UCSB, Stanford, UC San Diego, the University of Minnesota and the University of Massachusetts Amherst. It includes 11 researchers, six from UCSB, who work in four groups. One, led by Paul McIntyre, an associate professor of materials science and engineering at Stanford, is developing dielectrics (insulating materials). It includes Palmstrøm, UC San Diego Chemistry Professor Andrew Kummel and two members of the UCSB Materials faculty, Professor Chris Van de Walle and Associate Professor Susanne Stemmer. The device design group is lead by UC San Diego electrical and computer engineering professor Yuan Taur, and includes his colleague Peter Asbeck as well as UMass ECE Professor Max Fischetti. Device fabrication is led by Mark Rodwell in collaboration with UCSB Materials Professor Art Gossard.

The integration group, led by Palmstrøm, includes Asbeck, Stemmer, McIntyre and Stanford ECE Professor James Harris. UCSB’s nanofabrication laboratory is the center’s main venue for testing theory and (hopefully) coming up with devices that work.

The goal of all this brainpower and advanced fabrication sounds uncomplicated: To develop technology that combines the virtues of silicon and nonclassical materials. Silicon is strong, it’s relatively cheap and the industry is used to working with it. III-V semiconductors are fragile and expensive, but fast. New dielectrics, such as hafnium oxide, do not need to be proportionally as thin as silicon dioxide under scaling laws. Gate lengths thus can be shorter. Put all this together and you get faster, smaller transistors.

Trouble at the Interface

“UCSB has established a reputation around the world for being perhaps the best place for III-V materials and device fabrication using molecular-beam epitaxy,” McIntyre says.

Only it’s not that easy. The basic problem is that Rodwell, Palmstrøm, McIntyre and their colleagues, along with much of the semiconductor industry, are trying to improve on a model that, within its limits, is just about perfect. Any change makes the model more complex and introduces potential flaws. For instance, silicon not only is ideal for making the large, ultra-flat wafers demanded by the industry, it also bonds cleanly with its insulator, silicon dioxide. There are “no broken bonds, no free electrons dangling around,” Rodwell says. When such imperfections do appear, they can be erased through passivation, a process in which hydrogen atoms bond to stray electrons. Grafting hafnium oxide to silicon is trickier. The interface at the atomic level is not as close a match, and there are more dangling bonds to interfere with electron flow. Stemmer says this problem can be solved by separating the hafnium oxide from the silicon with a thin film – “just a few atomic layers” – of silicon dioxide. But no such fix is available with non-silicon semiconductors.

“Interfacing III-V semiconductors and oxides is incredibly difficult,” says Stemmer, who examines interfaces using atomic resolution imaging techniques. Researchers have not come up with a way to passivize these zones, she says, nor have they had much luck getting the transistor gates to close (in effect the device is stuck in the “on” position). Moreover, says McIntyre, III-V compounds tend not to behave well in the presence of oxygen. Put silicon next to silicon dioxide and the worst you get is more silicon dioxide. Expose gallium arsenide to an oxide, he says, and you get something much messier. “Gallium will be removed from the channel and excess arsenic will be left behind,” McIntyre says. This “creates a huge number of defects in the channel.” Another non-silicon semiconductor, germanium, also has “lots of problems,” says the theorist Van de Walle. For instance, it forms dangling bonds that are negatively charged and thus cannot be passivized with hydrogen.

III-V Integrated Circuit

III-V Integrated circuit.

Four “Miracles” Needed?

Rodwell sums up the task ahead as requiring four “miracles.” The first is to create “a decent dielectric interface.” The second is to figure out how to grow nonclassical material on a silicon wafer. The third is to make the new transistor work properly, given that the lighter and more mobile electrons are consequently larger (under quantum theory) and harder to keep in their channels. The fourth is not exactly a miracle “but just extremely hard work,” he says: “Someone has to build the transistors, and that’s me.”

But if the challenge looms large, so does the hope that the CMOS center’s resources might be equal to it. McIntyre says the group benefits from a “very well integrated team” whose expertise covers the bases from theory to production, advanced microscopy and other instrumentation, and a focus on the key problem of growing metal oxides. He also cites the crucial role of UCSB’s Nanofabrication Facility, a part of the National Nanotechnology Nanostructure Network. “UCSB has established a reputation around the world for being perhaps the best place for III-V materials and device fabrication using molecular-beam epitaxy,” he says. (Molecular-beam epitaxy, or MBE, is a high-vacuum method of growing thin crystalline films). He says UCSB’s III-V focus complements the more “silicon-centric” Stanford.

As for the notion that semiconductor technology is finally hitting the wall, Van de Walle says this is nothing new. “People have been saying we’re getting close for 20 years now, but whenever they say that, someone comes up with an approach that actually stretches the potential of CMOS technology.” Palmstrøm is not sure if the new research effort will succeed. But that doesn’t dampen his enthusiasm. “Scientifically and technologically,” he says, “it’s a fantastic challenge.”